Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) or a flash memory, both of which use charge to store information.
A more recent development in semiconductor memory devices involves spin electronics, which combines semiconductor technology and magnetic materials and devices. The spins of electrons, through their magnetic moments, rather than the charge of the electrons, is used to indicate the presence of a “1” or “0”. One such spin electronic device is a magnetic random access memory (MRAM) device 100, as shown in FIG. 1, which includes conductive lines (wordlines WL and bitlines BL) positioned in a different direction, e.g., perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack or magnetic tunnel junction (MTJ) 102, which functions as a magnetic memory cell. FIG. 1 shows a perspective view of a portion of a prior art cross-point MRAM array 100. The MRAM device 100 includes a semiconductor wafer comprising a workpiece (not shown). The workpiece has a first insulating layer (also not shown) deposited thereon, and a plurality of first conductive lines or wordlines WL is formed within the first insulating layer, e.g., in a first wiring level. The wordlines WL may comprise copper, aluminum, combinations thereof, and/or other metals, for example.
In a cross-point magnetic memory device 100, each memory cell or magnetic tunnel junction (MTJ) 102 is disposed over and abuts one wordline WL, as shown. The MTJ 102 of a magnetoresistive memory comprises three layers: ML1, TL and ML2. The MTJ 102 includes a first magnetic layer ML1 disposed over and abutting the wordline WL. The first magnetic layer ML1 is often referred to as a fixed layer because its magnetic orientation is fixed. A tunnel layer or tunnel barrier layer TL comprising a thin dielectric layer is formed over the fixed layer ML1. A second magnetic layer ML2 is formed over the tunnel barrier layer TL. The second magnetic layer ML2 is often referred to as a free layer because its magnetic orientation can be switched along one of two directions depending on the logic state of the memory cell. The first and second magnetic layers ML1 and ML2 may comprise one or more material layers, for example.
Each MTJ 102 has a second conductive line or bitline BL disposed over and abutting the second magnetic layer ML2, as shown in FIG. 1, wherein the bitline BL is positioned in a direction different from the direction of the wordline WL, e.g., the bitlines BL may be orthogonal to the wordlines WL. An array 100 of magnetic memory cells 102 comprises a plurality of wordlines WL running parallel to one another in a first direction, a plurality of bitlines BL running parallel to one another in a second direction, the second direction being different from the first direction, and a plurality of MTJ's 102 disposed between each wordline WL and bitline BL. While the bitlines BL are shown on top and the wordlines WL are shown on bottom of the array 100, alternatively, the wordlines WL may be disposed on the top of the array and the bitlines BL may be disposed on the bottom of the array, for example.
Either one of the first or second magnetic layers ML1 and ML2 may comprise a hard magnetic material (and is the fixed layer), and the other comprises a soft magnetic material (and is the free layer), although in the discussion herein, the first magnetic layer ML1 comprises the hard magnetic material, and the second magnetic layer ML2 comprises the soft magnetic material. The value of the resistance of the cell or MTJ 102 depends on the way in which the magnetic moment of the soft magnetic layer ML2 is oriented in relation to the magnetic moment of the hard magnetic layer ML1. The resistance of the magnetic memory cell 102 depends on the moment's relative alignment. The resistance Rc is usually lower if the magnetic layers have parallel magnetic orientations. For example, if the first and second magnetic layers ML1 and ML2 are oriented in the same direction, as shown in FIG. 2B, the cell resistance Rc is low. If the first and second magnetic layers ML1 and ML2 are oriented in opposite directions, shown in FIG. 2C, the cell resistance Rc is high. These two states of the cell are used to store digital information (a logic “1” or “0”, high or low resistance, or vice versa).
The hard magnetic layer ML1 is usually oriented once during manufacturing. The information of the cell 102 is stored in the soft magnetic layer ML2. As shown in FIG. 2A, the currents IWL and IBL through the wordline WL and bitline BL, respectively, provide the magnetic field that is necessary to store information in the soft magnetic layer ML2. The superimposed magnetic fields of the bitline BL and wordline WL currents have the ability to switch the magnetic moment of the soft magnetic layer ML2 and change the memory state of the cell 102.
An advantage of MRAM devices compared to traditional semiconductor memory devices such as dynamic random access memory (DRAM) devices is that MRAM devices are non-volatile. For example, a personal computer (PC) utilizing MRAM devices would not have a long “boot-up” time as with conventional PCs that utilize DRAM devices. Also, an MRAM device does not need to be powered up and has the capability of “remembering” the stored data (also referred to as a non-volatile memory). MRAM devices have the capability to provide the density of DRAM devices and the speed of static random access memory (SRAM) devices, in addition to non-volatility. Therefore, MRAM devices have the potential to replace flash memory, DRAM and SRAM devices in electronic applications where memory devices are needed in the future.
Because MRAM devices operate differently than traditional memory devices, they introduce design and manufacturing challenges. For example, the materials and processing techniques for manufacturing magnetic tunnel junction (MTJ) memory cells must be compatible with conventional complementary metal oxide semiconductor (CMOS) processing, because the MTJ memory cells are built over substrates comprising CMOS circuits that are used to read and write the state of the MTJ memory cells. Manganese (Mn) may be used in one of the layers of the bottom magnetic layer ML1, for example, for an anti-ferromagnetic layer, which is used to exchange bias the corresponding ferromagnetic reference layer for the purposes of fixing its magnetic moment in a particular direction set by the exchange bias field, as described in U.S. Pat. No. 5,650,958 entitled “Magnetic Tunnel Junctions With Controlled Magnetic Response,” issued on Jul. 22, 1997 to Gallagher et al., and U.S. Pat. No. 5,841,692, entitled, “Magnetic Tunnel Junction Device With Antiferromagnetically Coupled Pinned Layer”, issued on Nov. 24, 1998 to Gallagher et al., which are incorporated herein by reference. When heated to temperatures above about 350 degrees C., or lower or higher than 350 degrees C., depending on the composition of the manganese containing layer, manganese can diffuse into other layers of an MTJ memory cell, causing deterioration of various parts of the MTJ memory cell. For example, it is possible that the magnetic reference system may be weakened or, more likely, the Mn diffuses to or even through the tunnel barrier which can result in diminished magnetoresistance and/or lowered resistance, effectively destroying the functioning of the MTJ memory cell.
Another problem confronted in MRAM manufacturing is Neel coupling between nearby magnetic material layers. Neel coupling is ferromagnetic coupling or a magnetic interaction resulting from layers which have rough surfaces, whereby magnetic dipole fields arising from the first surface of one ferromagnetic layer interact with the second surface for a neighboring ferromagnetic layer. This coupling is also referred to as orange peel coupling in the art. Neel coupling results in a resistive memory element that is magnetically asymmetrical and therefore, favors one state of the memory over the other state, making the memory device difficult to operate. When large Neel coupling is present, the MTJ memory cell may require larger fields to switch or change its state.
What is needed in the art is an MTJ design that has a high degree of thermal stability, with reduced Neel coupling.